The present invention relates generally to the field of telecommunications, and in particular to adaptive pointer management for circuit emulation service.
Circuit emulation is a service by which synchronous circuits are carried across an asynchronous Packet Switch Network (PSN). The circuit emulation service over Asynchronous Transfer Mode (ATM) networks has been standardized and implemented. Circuit emulation over a regular packet network running over the Internet Protocol, or over Ethernet media or similar networks, is becoming more important, as PSNs are becoming predominant.
Circuit emulation has two distinct components; the adaptation of the circuit data into a packet stream at the sender, and the conversion of the circuit emulation stream back into a synchronous circuit at the receiver. The circuit emulation receiver logic requires a buffering mechanism to account for delay variation in the packet stream carrying the emulated circuit. This buffering mechanism is generically referred to as a “jitter buffer”. The sender sends the packet stream at a rate dictated by a sender clock. In many cases, the receiver does not have the sender clock available.
The receiver has control over the speed with which it empties the jitter buffer, by either controlling the outgoing circuit clock on its side, or by other means. If the receiver clock is faster than the sender clock, the jitter buffer will slowly become empty, as it is being filled slower than it is being emptied. Once the buffer empties, the receiver will no longer have circuit data, and errors will occur. Therefore, there is a need to have a way to reconstruct the sender clock on the receiver side. The common practice is to monitor the fill level of the jitter buffer (explained below), and adapt the frequency of a controlled oscillator accordingly. This task is challenging, as there are strict restrictions within the standards on the quality and characteristics of a circuit clock. Since the delay variations of packet arrival across the PSN can be much larger than the ATM cell delay variations, the challenge of adaptive clock recovery across a PSN is larger.
The synchronous optical network (SONET) standard is a standard for optical telecommunications transport prepared by the American National Standards Institute (ANSI). Similarly, the synchronous digital hierarchy (SDH) standard is the international standard prepared by the International Telecommunication Union (ITU). Below we refer only to SONET technology, with the understanding that the present invention is applicable to SDH technology as well.
One of the benefits of SONET is that it can carry large payloads (above 50 Mbps) in synchronous transport signals (STS-N), as well as accommodating the lower rate plesiochronous digital hierarchy (PDH) signals, including T1, T3, E1, E3 etc. To achieve this capability, the basic SONET synchronous transport signal (STS−1) can be sub-divided into smaller components or structures, known as Virtual Tributaries (VTs), for the purpose of transporting and switching PDH payloads.
SONET utilizes payload pointers to carry the signal. A payload pointer gives the location of the beginning of the payload within the SONET structure. Differences in phase and frequency between two SONET NEs (Network Elements) can be handled by the use of payload pointers. If the sending SONET NE is faster than the receiving NE, the receiving NE will introduce a negative pointer adjustment (PA) and shift the payload ahead by one byte or 8 bits (N bytes for STS-Nc). This allows the receiving NE to keep up with the sending NE without loss of information. Similarly, if the sending NE is slower than the receiving NE, the receiving NE will introduce a positive pointer adjustment of one byte (N bytes for STS-Nc).
SONET emulation technology has a variant of adaptive clock recovery called Adaptive Pointer Management (APM). APM does not directly change the clock at the receiver side to accommodate for differences between sender and receiver clocks, but rather generates pointer adjustments that change effectively the rate at which the receiver reads the information from the jitter buffer, and plays it out on the circuit data. Using conventional SONET methods, PAs are converted to clock differences by devices called “Mappers”. This is further explained in FIG. 1.
FIG. 1 describes a simplified SONET emulation system 100 with APM. System 100 comprises a sender 102 connected across a packet switch network or an ATM network to a receiver 130. Sender 102 includes either a SONET interface 104, a PDH interface 106, or both. Sender 102 further includes a SONET line interface unit (LWU) 110, a SONET framer 112, a PDH LIU 114 and a PDH mapper 116 and a Host CPU 128. Host CPU 128 runs the various software tasks of sender 102, including configuration and performance monitoring tasks. Mapper 116 is responsible for mapping the PDH signals into SONET channels. Sender 102 further includes a packetizer 118 that extracts the SONET information from either SONET framer 112 or mapper 116 or both, through a multiplexer (MUX) 120. The sender encapsulates the different SONET channels into packet streams, and sends the packets through an output sender interface 122 across the PSN or ATM network. Each packet carries a sequence number to allow the receiver to assemble the incoming stream in the order it has been sent, and to identify lost packets. The sender is driven by a system clock 124 denoted Clock-S. Receiver 130, which includes and is driven by a Clock-R 132 that is not synchronized to the sender clock, and which may therefore operate at a different frequency, receives the packets from the sender through an input receiver interface 134. Arriving packets are read from the packet interface and placed in a jitter buffer 136. The sequence number of incoming packets is used to identify lost, duplicated, or mis-ordered packets. Packets are placed in the jitter buffer in the order they were sent. If one or more packets are lost, the jitter buffer indicates the loss. For example, if packets with sequence numbers 54, 55, 55, 52, 53, 56, 58, 59, 60, arrive at the receiver, the receiver would re-order these packets to the correct order 52 to 60, ignoring the duplicated 55th packet, and indicating that packet 57 was lost. Separate jitter buffers are maintained for each emulated channel. A de-packetizer 138 in the receiver extracts information from the jitter buffer, and plays it out onto either a SONET framer 140 or a mapper 142 (both included in the receiver), at a rate determined by Clock-R. Framer 140 sends the SONET signal through a SONET LIU 144 to a SONET interface 146, which exits the receiver. The mapper extracts the PDH information from the SONET containers, and sends it through a PDH LIU 148 to a PDH interface 150, which also exits the receiver. An APM module 160 monitors the fill level of the jitter buffer for each channel, and generates positive or negative PAs to maintain the differences in Clock-R and Clock-S. The PAs are played out to the framer interface or to the mapper interface. The standard SONET framer and mapper interfaces support PA indications. PAs are included in the SONET signal sent on the SONET interface. PAs are converted into change of clock for each PDH channel in the standard mapper block. Host CPU 150 runs the software tasks of receiver 130.
The SONET pointer adjustments mechanism is but one technique to accommodate for differences in NE clocks. Another widely used technique is called bit-stuffing, which multiplexes low rate PDH signals into higher rate trunks. Examples of bit-stuffing include multiplexing T1 into a T3 trunk, mapping T1 into SONET, and mapping T3 into SONET. The bit-stuffing technique encapsulates the lower rate signal into a higher rate container. The higher rate container includes opportunity bits and opportunity control bits. The opportunity control bits indicate whether the opportunity bits carry data or whether they should be ignored. Consequently, the NE mapping the lower rate PDH service into a higher rate multiplex uses more opportunity bits if the rate of the incoming lower rate signal is driven by a clock faster than the NE clock, and uses less opportunity bits if the lower rate signal is driven by a slower clock.
The existing techniques for adjusting differences in NE clocks are therefore dedicated in the sense that they are quite inflexible. Different applications require different systems. In existing APM, the pointer adjustment is not optimized, There is therefore a need for flexible and optimized methods and systems that can be applied to a variety of application where NE clock adjustment is required.